<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Thu Nov 21 11:06:17 2024</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2020.2 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>5a6350858e214efb83cf00bd2c2768a4</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>dd59c7f2cd205b6795439105847f3e76</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>dd59c7f2cd205b6795439105847f3e76</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7z010</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>zynq</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>clg400</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i5-13500H</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>3187 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>16.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>applyrsbmultiautomationdialog_checkbox_tree=2</TD>
   <TD>basedialog_cancel=10</TD>
   <TD>basedialog_ok=24</TD>
   <TD>basedialog_yes=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>cmdmsgdialog_messages=1</TD>
   <TD>cmdmsgdialog_ok=4</TD>
   <TD>coretreetablepanel_core_tree_table=23</TD>
   <TD>customizecoredialog_ip_location=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>ddrconfigtreetablepanel_ddr_config_tree_table=4</TD>
   <TD>filesetpanel_file_set_panel_tree=14</TD>
   <TD>flownavigatortreepanel_flow_navigator_tree=22</TD>
   <TD>fpgachooser_fpga_table=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>fpgachooser_package=1</TD>
   <TD>fpgachooser_speed=1</TD>
   <TD>gictreetablepanel_gic_tree_table=4</TD>
   <TD>hfiltertoolbar_hide_all=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>hfiltertoolbar_show_all=1</TD>
   <TD>mainmenumgr_checkpoint=1</TD>
   <TD>mainmenumgr_file=4</TD>
   <TD>mainmenumgr_ip=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_project=3</TD>
   <TD>mainmenumgr_text_editor=2</TD>
   <TD>miotablepagepanel_mio_table=9</TD>
   <TD>miotablepagepanel_mio_table_parameter=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_create_top_hdl=1</TD>
   <TD>pacommandnames_generate_composite_file=4</TD>
   <TD>pacommandnames_new_project=1</TD>
   <TD>pacommandnames_open_project=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_save_rsb_design=10</TD>
   <TD>paviews_project_summary=3</TD>
   <TD>projectnamechooser_choose_project_location=1</TD>
   <TD>projectnamechooser_project_name=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_properties=1</TD>
   <TD>rdicommands_settings=1</TD>
   <TD>rsbapplyautomationbar_run_block_automation=3</TD>
   <TD>rsbapplyautomationbar_run_connection_automation=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>saveprojectutils_save=1</TD>
   <TD>simpleoutputproductdialog_generate_output_products_immediately=4</TD>
   <TD>simpleoutputproductdialog_synthesize_design_globally=1</TD>
   <TD>syntheticagettingstartedview_recent_projects=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>systembuilderview_add_ip=3</TD>
   <TD>systemtreeview_system_tree=2</TD>
   <TD>tclconsoleview_tcl_console_code_editor=1</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>coreview=7</TD>
   <TD>createblockdesign=2</TD>
   <TD>createtophdl=1</TD>
   <TD>customizecore=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>customizersbblock=17</TD>
   <TD>editproperties=1</TD>
   <TD>editundo=1</TD>
   <TD>managecompositetargets=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>newproject=1</TD>
   <TD>openblockdesign=4</TD>
   <TD>openproject=1</TD>
   <TD>runbitgen=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>runimplementation=3</TD>
   <TD>runsynthesis=2</TD>
   <TD>saversbdesign=10</TD>
   <TD>toolssettings=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>viewtaskimplementation=2</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=3</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=0</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=3</TD>
   <TD>export_simulation_ies=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=3</TD>
   <TD>export_simulation_questa=3</TD>
   <TD>export_simulation_riviera=3</TD>
   <TD>export_simulation_vcs=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=3</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=0</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=2</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=1</TD>
   <TD>totalsynthesisruns=1</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bibuf=130</TD>
    <TD>bufg=1</TD>
    <TD>carry4=20</TD>
    <TD>fdce=105</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=4198</TD>
    <TD>fdse=259</TD>
    <TD>gnd=294</TD>
    <TD>lut1=252</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2=329</TD>
    <TD>lut3=967</TD>
    <TD>lut4=750</TD>
    <TD>lut5=775</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6=1553</TD>
    <TD>muxf7=4</TD>
    <TD>ps7=1</TD>
    <TD>ramb36e1=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramd32=468</TD>
    <TD>rams32=156</TD>
    <TD>srl16e=198</TD>
    <TD>srlc32e=182</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=265</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bibuf=130</TD>
    <TD>bufg=1</TD>
    <TD>carry4=20</TD>
    <TD>fdce=105</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=4198</TD>
    <TD>fdse=259</TD>
    <TD>gnd=294</TD>
    <TD>lut1=252</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2=329</TD>
    <TD>lut3=967</TD>
    <TD>lut4=750</TD>
    <TD>lut5=775</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6=1553</TD>
    <TD>muxf7=4</TD>
    <TD>ps7=1</TD>
    <TD>ram32m=78</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36e1=2</TD>
    <TD>srl16e=198</TD>
    <TD>srlc32e=182</TD>
    <TD>vcc=265</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>phys_opt_design_post_place</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-aggressive_hold_fix=default::[not_specified]</TD>
    <TD>-bram_register_opt=default::[not_specified]</TD>
    <TD>-clock_opt=default::[not_specified]</TD>
    <TD>-critical_cell_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-critical_pin_opt=default::[not_specified]</TD>
    <TD>-directive=default::[not_specified]</TD>
    <TD>-dsp_register_opt=default::[not_specified]</TD>
    <TD>-effort_level=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fanout_opt=default::[not_specified]</TD>
    <TD>-hold_fix=default::[not_specified]</TD>
    <TD>-insert_negative_edge_ffs=default::[not_specified]</TD>
    <TD>-multi_clock_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-placement_opt=default::[not_specified]</TD>
    <TD>-restruct_opt=default::[not_specified]</TD>
    <TD>-retime=default::[not_specified]</TD>
    <TD>-rewire=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-shift_register_opt=default::[not_specified]</TD>
    <TD>-uram_register_opt=default::[not_specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
    <TD>-vhfn=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-cell_types=default::all</TD>
    <TD>-clocks=default::[not_specified]</TD>
    <TD>-exclude_cells=default::[not_specified]</TD>
    <TD>-include_cells=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bram_ports_augmented=0</TD>
    <TD>bram_ports_newly_gated=0</TD>
    <TD>bram_ports_total=4</TD>
    <TD>flow_state=default</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_augmented=0</TD>
    <TD>slice_registers_newly_gated=0</TD>
    <TD>slice_registers_total=4440</TD>
    <TD>srls_augmented=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>srls_newly_gated=0</TD>
    <TD>srls_total=323</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>IP_Integrator/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bdsource=SBD</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>maxhierdepth=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>numblks=38</TD>
    <TD>numhdlrefblks=0</TD>
    <TD>numhierblks=8</TD>
    <TD>numhlsblks=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>numnonxlnxblks=0</TD>
    <TD>numpkgbdblks=0</TD>
    <TD>numreposblks=30</TD>
    <TD>numsysgenblks=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>synth_mode=Global</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=BlockDiagram</TD>
    <TD>x_ipname=bd_48ac</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.00.a</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>IP_Integrator/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bdsource=USER</TD>
    <TD>core_container=NA</TD>
    <TD>da_axi4_cnt=2</TD>
    <TD>da_bram_cntlr_cnt=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>da_ps7_cnt=2</TD>
    <TD>iptotal=1</TD>
    <TD>maxhierdepth=0</TD>
    <TD>numblks=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>numhdlrefblks=0</TD>
    <TD>numhierblks=0</TD>
    <TD>numhlsblks=0</TD>
    <TD>numnonxlnxblks=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>numpkgbdblks=0</TD>
    <TD>numreposblks=7</TD>
    <TD>numsysgenblks=0</TD>
    <TD>synth_mode=Global</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=BlockDiagram</TD>
    <TD>x_ipname=design_1</TD>
    <TD>x_ipvendor=xilinx.com</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipversion=1.00.a</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_bram_ctrl/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_bram_addr_width=11</TD>
    <TD>c_bram_inst_mode=EXTERNAL</TD>
    <TD>c_ecc=0</TD>
    <TD>c_ecc_onoff_reset_value=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_ecc_type=0</TD>
    <TD>c_family=zynq</TD>
    <TD>c_fault_inject=0</TD>
    <TD>c_memory_depth=2048</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rd_cmd_optimization=0</TD>
    <TD>c_read_latency=1</TD>
    <TD>c_s_axi_addr_width=13</TD>
    <TD>c_s_axi_ctrl_addr_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_ctrl_data_width=32</TD>
    <TD>c_s_axi_data_width=32</TD>
    <TD>c_s_axi_id_width=1</TD>
    <TD>c_s_axi_protocol=AXI4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_supports_narrow_burst=0</TD>
    <TD>c_single_port_bram=1</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipcorerevision=4</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=axi_bram_ctrl</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipproduct=Vivado 2020.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=4.1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_bram_ctrl/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_bram_addr_width=11</TD>
    <TD>c_bram_inst_mode=EXTERNAL</TD>
    <TD>c_ecc=0</TD>
    <TD>c_ecc_onoff_reset_value=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_ecc_type=0</TD>
    <TD>c_family=zynq</TD>
    <TD>c_fault_inject=0</TD>
    <TD>c_memory_depth=2048</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rd_cmd_optimization=0</TD>
    <TD>c_read_latency=1</TD>
    <TD>c_s_axi_addr_width=13</TD>
    <TD>c_s_axi_ctrl_addr_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_ctrl_data_width=32</TD>
    <TD>c_s_axi_data_width=32</TD>
    <TD>c_s_axi_id_width=1</TD>
    <TD>c_s_axi_protocol=AXI4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_supports_narrow_burst=0</TD>
    <TD>c_single_port_bram=1</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipcorerevision=4</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=axi_bram_ctrl</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipproduct=Vivado 2020.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=4.1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>bd_48ac/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=14</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=smartconnect</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>blk_mem_gen_v8_4_4/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addra_width=32</TD>
    <TD>c_addrb_width=32</TD>
    <TD>c_algorithm=1</TD>
    <TD>c_axi_id_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_slave_type=0</TD>
    <TD>c_axi_type=1</TD>
    <TD>c_byte_size=8</TD>
    <TD>c_common_clk=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_count_18k_bram=0</TD>
    <TD>c_count_36k_bram=2</TD>
    <TD>c_ctrl_ecc_algo=NONE</TD>
    <TD>c_default_data=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_disable_warn_bhv_coll=0</TD>
    <TD>c_disable_warn_bhv_range=0</TD>
    <TD>c_elaboration_dir=./</TD>
    <TD>c_en_deepsleep_pin=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_ecc_pipe=0</TD>
    <TD>c_en_rdaddra_chg=0</TD>
    <TD>c_en_rdaddrb_chg=0</TD>
    <TD>c_en_safety_ckt=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_shutdown_pin=0</TD>
    <TD>c_en_sleep_pin=0</TD>
    <TD>c_enable_32bit_address=1</TD>
    <TD>c_est_power_summary=Estimated Power for IP     _     10.7492 mW</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=zynq</TD>
    <TD>c_has_axi_id=0</TD>
    <TD>c_has_ena=1</TD>
    <TD>c_has_enb=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_injecterr=0</TD>
    <TD>c_has_mem_output_regs_a=0</TD>
    <TD>c_has_mem_output_regs_b=0</TD>
    <TD>c_has_mux_output_regs_a=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_mux_output_regs_b=0</TD>
    <TD>c_has_regcea=0</TD>
    <TD>c_has_regceb=0</TD>
    <TD>c_has_rsta=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_rstb=1</TD>
    <TD>c_has_softecc_input_regs_a=0</TD>
    <TD>c_has_softecc_output_regs_b=0</TD>
    <TD>c_init_file=NONE</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_init_file_name=no_coe_file_loaded</TD>
    <TD>c_inita_val=0</TD>
    <TD>c_initb_val=0</TD>
    <TD>c_interface_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_load_init_file=0</TD>
    <TD>c_mem_type=2</TD>
    <TD>c_mux_pipeline_stages=0</TD>
    <TD>c_prim_type=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_read_depth_a=2048</TD>
    <TD>c_read_depth_b=2048</TD>
    <TD>c_read_latency_a=1</TD>
    <TD>c_read_latency_b=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_read_width_a=32</TD>
    <TD>c_read_width_b=32</TD>
    <TD>c_rst_priority_a=CE</TD>
    <TD>c_rst_priority_b=CE</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rstram_a=0</TD>
    <TD>c_rstram_b=0</TD>
    <TD>c_sim_collision_check=ALL</TD>
    <TD>c_use_bram_block=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_byte_wea=1</TD>
    <TD>c_use_byte_web=1</TD>
    <TD>c_use_default_data=0</TD>
    <TD>c_use_ecc=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_softecc=0</TD>
    <TD>c_use_uram=0</TD>
    <TD>c_wea_width=4</TD>
    <TD>c_web_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_write_depth_a=2048</TD>
    <TD>c_write_depth_b=2048</TD>
    <TD>c_write_mode_a=WRITE_FIRST</TD>
    <TD>c_write_mode_b=WRITE_FIRST</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_write_width_a=32</TD>
    <TD>c_write_width_b=32</TD>
    <TD>c_xdevicefamily=zynq</TD>
    <TD>core_container=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=4</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipname=blk_mem_gen</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipversion=8.4</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>proc_sys_reset/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aux_reset_high=0</TD>
    <TD>c_aux_rst_width=1</TD>
    <TD>c_ext_reset_high=0</TD>
    <TD>c_ext_rst_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=zynq</TD>
    <TD>c_num_bus_rst=1</TD>
    <TD>c_num_interconnect_aresetn=1</TD>
    <TD>c_num_perp_aresetn=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_perp_rst=1</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=13</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=proc_sys_reset</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=5.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>proc_sys_reset/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aux_reset_high=0</TD>
    <TD>c_aux_rst_width=4</TD>
    <TD>c_ext_reset_high=0</TD>
    <TD>c_ext_rst_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=zynq</TD>
    <TD>c_num_bus_rst=1</TD>
    <TD>c_num_interconnect_aresetn=1</TD>
    <TD>c_num_perp_aresetn=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_perp_rst=1</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=13</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=proc_sys_reset</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=5.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>processing_system7_v5.5_user_configuration/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>pcw_apu_clk_ratio_enable=6:2:1</TD>
    <TD>pcw_apu_peripheral_freqmhz=666.666666</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_armpll_ctrl_fbdiv=40</TD>
    <TD>pcw_can0_grp_clk_enable=0</TD>
    <TD>pcw_can0_peripheral_clksrc=External</TD>
    <TD>pcw_can0_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_can0_peripheral_freqmhz=-1</TD>
    <TD>pcw_can1_grp_clk_enable=0</TD>
    <TD>pcw_can1_peripheral_clksrc=External</TD>
    <TD>pcw_can1_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_can1_peripheral_freqmhz=-1</TD>
    <TD>pcw_can_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_can_peripheral_freqmhz=100</TD>
    <TD>pcw_cpu_cpu_pll_freqmhz=1333.333</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_cpu_peripheral_clksrc=ARM PLL</TD>
    <TD>pcw_crystal_peripheral_freqmhz=33.333333</TD>
    <TD>pcw_dci_peripheral_clksrc=DDR PLL</TD>
    <TD>pcw_dci_peripheral_freqmhz=10.159</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ddr_ddr_pll_freqmhz=1066.667</TD>
    <TD>pcw_ddr_hpr_to_critical_priority_level=15</TD>
    <TD>pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32)</TD>
    <TD>pcw_ddr_lpr_to_critical_priority_level=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ddr_peripheral_clksrc=DDR PLL</TD>
    <TD>pcw_ddr_port0_hpr_enable=0</TD>
    <TD>pcw_ddr_port1_hpr_enable=0</TD>
    <TD>pcw_ddr_port2_hpr_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ddr_port3_hpr_enable=0</TD>
    <TD>pcw_ddr_write_to_critical_priority_level=2</TD>
    <TD>pcw_ddrpll_ctrl_fbdiv=32</TD>
    <TD>pcw_enet0_enet0_io=MIO 16 .. 27</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_enet0_grp_mdio_enable=1</TD>
    <TD>pcw_enet0_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_enet0_peripheral_enable=1</TD>
    <TD>pcw_enet0_peripheral_freqmhz=1000 Mbps</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_enet0_reset_enable=0</TD>
    <TD>pcw_enet1_grp_mdio_enable=0</TD>
    <TD>pcw_enet1_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_enet1_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_enet1_peripheral_freqmhz=1000 Mbps</TD>
    <TD>pcw_enet1_reset_enable=0</TD>
    <TD>pcw_enet_reset_polarity=Active Low</TD>
    <TD>pcw_fclk0_peripheral_clksrc=IO PLL</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_fclk1_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fclk2_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fclk3_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fpga0_peripheral_freqmhz=50</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_fpga1_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga2_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga3_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga_fclk0_enable=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_fpga_fclk1_enable=0</TD>
    <TD>pcw_fpga_fclk2_enable=0</TD>
    <TD>pcw_fpga_fclk3_enable=0</TD>
    <TD>pcw_ftm_cti_in0=DISABLED</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ftm_cti_in1=DISABLED</TD>
    <TD>pcw_ftm_cti_in2=DISABLED</TD>
    <TD>pcw_ftm_cti_in3=DISABLED</TD>
    <TD>pcw_ftm_cti_out0=DISABLED</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ftm_cti_out1=DISABLED</TD>
    <TD>pcw_ftm_cti_out2=DISABLED</TD>
    <TD>pcw_ftm_cti_out3=DISABLED</TD>
    <TD>pcw_gpio_emio_gpio_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_gpio_mio_gpio_enable=0</TD>
    <TD>pcw_gpio_peripheral_enable=0</TD>
    <TD>pcw_i2c0_grp_int_enable=0</TD>
    <TD>pcw_i2c0_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_i2c0_reset_enable=0</TD>
    <TD>pcw_i2c1_grp_int_enable=0</TD>
    <TD>pcw_i2c1_peripheral_enable=0</TD>
    <TD>pcw_i2c1_reset_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_i2c_reset_polarity=Active Low</TD>
    <TD>pcw_io_io_pll_freqmhz=1000.000</TD>
    <TD>pcw_iopll_ctrl_fbdiv=30</TD>
    <TD>pcw_irq_f2p_mode=DIRECT</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_m_axi_gp0_freqmhz=50</TD>
    <TD>pcw_m_axi_gp1_freqmhz=10</TD>
    <TD>pcw_nand_cycles_t_ar=1</TD>
    <TD>pcw_nand_cycles_t_clr=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nand_cycles_t_rc=11</TD>
    <TD>pcw_nand_cycles_t_rea=1</TD>
    <TD>pcw_nand_cycles_t_rr=1</TD>
    <TD>pcw_nand_cycles_t_wc=11</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nand_cycles_t_wp=1</TD>
    <TD>pcw_nand_grp_d8_enable=0</TD>
    <TD>pcw_nand_peripheral_enable=0</TD>
    <TD>pcw_nor_cs0_t_ceoe=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_cs0_t_pc=1</TD>
    <TD>pcw_nor_cs0_t_rc=11</TD>
    <TD>pcw_nor_cs0_t_tr=1</TD>
    <TD>pcw_nor_cs0_t_wc=11</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_cs0_t_wp=1</TD>
    <TD>pcw_nor_cs0_we_time=0</TD>
    <TD>pcw_nor_cs1_t_ceoe=1</TD>
    <TD>pcw_nor_cs1_t_pc=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_cs1_t_rc=11</TD>
    <TD>pcw_nor_cs1_t_tr=1</TD>
    <TD>pcw_nor_cs1_t_wc=11</TD>
    <TD>pcw_nor_cs1_t_wp=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_cs1_we_time=0</TD>
    <TD>pcw_nor_grp_a25_enable=0</TD>
    <TD>pcw_nor_grp_cs0_enable=0</TD>
    <TD>pcw_nor_grp_cs1_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_grp_sram_cs0_enable=0</TD>
    <TD>pcw_nor_grp_sram_cs1_enable=0</TD>
    <TD>pcw_nor_grp_sram_int_enable=0</TD>
    <TD>pcw_nor_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_sram_cs0_t_ceoe=1</TD>
    <TD>pcw_nor_sram_cs0_t_pc=1</TD>
    <TD>pcw_nor_sram_cs0_t_rc=11</TD>
    <TD>pcw_nor_sram_cs0_t_tr=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_sram_cs0_t_wc=11</TD>
    <TD>pcw_nor_sram_cs0_t_wp=1</TD>
    <TD>pcw_nor_sram_cs0_we_time=0</TD>
    <TD>pcw_nor_sram_cs1_t_ceoe=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_sram_cs1_t_pc=1</TD>
    <TD>pcw_nor_sram_cs1_t_rc=11</TD>
    <TD>pcw_nor_sram_cs1_t_tr=1</TD>
    <TD>pcw_nor_sram_cs1_t_wc=11</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_sram_cs1_t_wp=1</TD>
    <TD>pcw_nor_sram_cs1_we_time=0</TD>
    <TD>pcw_override_basic_clock=0</TD>
    <TD>pcw_pcap_peripheral_clksrc=IO PLL</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_pcap_peripheral_freqmhz=200</TD>
    <TD>pcw_pjtag_peripheral_enable=0</TD>
    <TD>pcw_preset_bank0_voltage=LVCMOS 3.3V</TD>
    <TD>pcw_preset_bank1_voltage=LVCMOS 1.8V</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_qspi_grp_fbclk_enable=0</TD>
    <TD>pcw_qspi_grp_io1_enable=0</TD>
    <TD>pcw_qspi_grp_single_ss_enable=1</TD>
    <TD>pcw_qspi_grp_single_ss_io=MIO 1 .. 6</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_qspi_grp_ss1_enable=0</TD>
    <TD>pcw_qspi_internal_highaddress=0xFCFFFFFF</TD>
    <TD>pcw_qspi_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_qspi_peripheral_enable=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_qspi_peripheral_freqmhz=200</TD>
    <TD>pcw_qspi_qspi_io=MIO 1 .. 6</TD>
    <TD>pcw_s_axi_acp_freqmhz=10</TD>
    <TD>pcw_s_axi_gp0_freqmhz=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_s_axi_gp1_freqmhz=10</TD>
    <TD>pcw_s_axi_hp0_data_width=64</TD>
    <TD>pcw_s_axi_hp0_freqmhz=10</TD>
    <TD>pcw_s_axi_hp1_data_width=64</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_s_axi_hp1_freqmhz=10</TD>
    <TD>pcw_s_axi_hp2_data_width=64</TD>
    <TD>pcw_s_axi_hp2_freqmhz=10</TD>
    <TD>pcw_s_axi_hp3_data_width=64</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_s_axi_hp3_freqmhz=10</TD>
    <TD>pcw_sd0_grp_cd_enable=0</TD>
    <TD>pcw_sd0_grp_pow_enable=0</TD>
    <TD>pcw_sd0_grp_wp_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_sd0_peripheral_enable=0</TD>
    <TD>pcw_sd1_grp_cd_enable=0</TD>
    <TD>pcw_sd1_grp_pow_enable=0</TD>
    <TD>pcw_sd1_grp_wp_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_sd1_peripheral_enable=0</TD>
    <TD>pcw_sdio_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_sdio_peripheral_freqmhz=100</TD>
    <TD>pcw_single_qspi_data_mode=x4</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_smc_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_smc_peripheral_freqmhz=100</TD>
    <TD>pcw_spi0_grp_ss0_enable=0</TD>
    <TD>pcw_spi0_grp_ss1_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_spi0_grp_ss2_enable=0</TD>
    <TD>pcw_spi0_peripheral_enable=0</TD>
    <TD>pcw_spi1_grp_ss0_enable=0</TD>
    <TD>pcw_spi1_grp_ss1_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_spi1_grp_ss2_enable=0</TD>
    <TD>pcw_spi1_peripheral_enable=0</TD>
    <TD>pcw_spi_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_spi_peripheral_freqmhz=166.666666</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_tpiu_peripheral_clksrc=External</TD>
    <TD>pcw_tpiu_peripheral_freqmhz=200</TD>
    <TD>pcw_trace_grp_16bit_enable=0</TD>
    <TD>pcw_trace_grp_2bit_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_trace_grp_32bit_enable=0</TD>
    <TD>pcw_trace_grp_4bit_enable=0</TD>
    <TD>pcw_trace_grp_8bit_enable=0</TD>
    <TD>pcw_trace_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc0_clk0_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc0_clk0_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc0_clk1_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc0_clk1_peripheral_freqmhz=133.333333</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc0_clk2_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc0_clk2_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc0_peripheral_enable=0</TD>
    <TD>pcw_ttc1_clk0_peripheral_clksrc=CPU_1X</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc1_clk0_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc1_clk1_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc1_clk1_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc1_clk2_peripheral_clksrc=CPU_1X</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc1_clk2_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc1_peripheral_enable=0</TD>
    <TD>pcw_ttc_peripheral_freqmhz=50</TD>
    <TD>pcw_uart0_baud_rate=115200</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uart0_grp_full_enable=0</TD>
    <TD>pcw_uart0_peripheral_enable=1</TD>
    <TD>pcw_uart0_uart0_io=MIO 14 .. 15</TD>
    <TD>pcw_uart1_baud_rate=115200</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uart1_grp_full_enable=0</TD>
    <TD>pcw_uart1_peripheral_enable=0</TD>
    <TD>pcw_uart_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_uart_peripheral_freqmhz=100</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_adv_enable=0</TD>
    <TD>pcw_uiparam_ddr_al=0</TD>
    <TD>pcw_uiparam_ddr_bank_addr_count=3</TD>
    <TD>pcw_uiparam_ddr_bl=8</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_board_delay0=0.25</TD>
    <TD>pcw_uiparam_ddr_board_delay1=0.25</TD>
    <TD>pcw_uiparam_ddr_board_delay2=0.25</TD>
    <TD>pcw_uiparam_ddr_board_delay3=0.25</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_bus_width=32 Bit</TD>
    <TD>pcw_uiparam_ddr_cl=7</TD>
    <TD>pcw_uiparam_ddr_clock_0_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_clock_0_package_length=54.563</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_clock_0_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_clock_1_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_clock_1_package_length=54.563</TD>
    <TD>pcw_uiparam_ddr_clock_1_propogation_delay=160</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_clock_2_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_clock_2_package_length=54.563</TD>
    <TD>pcw_uiparam_ddr_clock_2_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_clock_3_length_mm=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_clock_3_package_length=54.563</TD>
    <TD>pcw_uiparam_ddr_clock_3_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_clock_stop_en=0</TD>
    <TD>pcw_uiparam_ddr_col_addr_count=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_cwl=6</TD>
    <TD>pcw_uiparam_ddr_device_capacity=2048 MBits</TD>
    <TD>pcw_uiparam_ddr_dq_0_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dq_0_package_length=104.5365</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dq_0_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dq_1_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dq_1_package_length=70.676</TD>
    <TD>pcw_uiparam_ddr_dq_1_propogation_delay=160</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dq_2_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dq_2_package_length=59.1615</TD>
    <TD>pcw_uiparam_ddr_dq_2_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dq_3_length_mm=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dq_3_package_length=81.319</TD>
    <TD>pcw_uiparam_ddr_dq_3_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dqs_0_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dqs_0_package_length=101.239</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_0_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dqs_1_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dqs_1_package_length=79.5025</TD>
    <TD>pcw_uiparam_ddr_dqs_1_propogation_delay=160</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_2_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dqs_2_package_length=60.536</TD>
    <TD>pcw_uiparam_ddr_dqs_2_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dqs_3_length_mm=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_3_package_length=71.7715</TD>
    <TD>pcw_uiparam_ddr_dqs_3_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_0=0.0</TD>
    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_1=0.0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_2=0.0</TD>
    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_3=0.0</TD>
    <TD>pcw_uiparam_ddr_dram_width=16 Bits</TD>
    <TD>pcw_uiparam_ddr_ecc=Disabled</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_enable=1</TD>
    <TD>pcw_uiparam_ddr_freq_mhz=533.333333</TD>
    <TD>pcw_uiparam_ddr_high_temp=Normal (0-85)</TD>
    <TD>pcw_uiparam_ddr_memory_type=DDR 3</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_partno=MT41J128M16 HA-125</TD>
    <TD>pcw_uiparam_ddr_row_addr_count=14</TD>
    <TD>pcw_uiparam_ddr_speed_bin=DDR3_1066F</TD>
    <TD>pcw_uiparam_ddr_t_faw=40.0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_t_ras_min=35.0</TD>
    <TD>pcw_uiparam_ddr_t_rc=48.75</TD>
    <TD>pcw_uiparam_ddr_t_rcd=7</TD>
    <TD>pcw_uiparam_ddr_t_rp=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_train_data_eye=1</TD>
    <TD>pcw_uiparam_ddr_train_read_gate=1</TD>
    <TD>pcw_uiparam_ddr_train_write_level=1</TD>
    <TD>pcw_uiparam_ddr_use_internal_vref=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_usb0_peripheral_enable=0</TD>
    <TD>pcw_usb0_peripheral_freqmhz=60</TD>
    <TD>pcw_usb0_reset_enable=0</TD>
    <TD>pcw_usb1_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_usb1_peripheral_freqmhz=60</TD>
    <TD>pcw_usb1_reset_enable=0</TD>
    <TD>pcw_usb_reset_polarity=Active Low</TD>
    <TD>pcw_use_cross_trigger=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_use_m_axi_gp0=1</TD>
    <TD>pcw_use_m_axi_gp1=0</TD>
    <TD>pcw_use_s_axi_acp=0</TD>
    <TD>pcw_use_s_axi_gp0=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_use_s_axi_gp1=0</TD>
    <TD>pcw_use_s_axi_hp0=0</TD>
    <TD>pcw_use_s_axi_hp1=0</TD>
    <TD>pcw_use_s_axi_hp2=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_use_s_axi_hp3=0</TD>
    <TD>pcw_wdt_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_wdt_peripheral_enable=0</TD>
    <TD>pcw_wdt_peripheral_freqmhz=133.333333</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>processing_system7_v5_5_processing_system7/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_dm_width=4</TD>
    <TD>c_dq_width=32</TD>
    <TD>c_dqs_width=4</TD>
    <TD>c_emio_gpio_width=64</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_emio_enet0=0</TD>
    <TD>c_en_emio_enet1=0</TD>
    <TD>c_en_emio_pjtag=0</TD>
    <TD>c_en_emio_trace=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_fclk_clk0_buf=TRUE</TD>
    <TD>c_fclk_clk1_buf=FALSE</TD>
    <TD>c_fclk_clk2_buf=FALSE</TD>
    <TD>c_fclk_clk3_buf=FALSE</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_gp0_en_modifiable_txn=1</TD>
    <TD>c_gp1_en_modifiable_txn=1</TD>
    <TD>c_include_acp_trans_check=0</TD>
    <TD>c_include_trace_buffer=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_irq_f2p_mode=DIRECT</TD>
    <TD>c_m_axi_gp0_enable_static_remap=0</TD>
    <TD>c_m_axi_gp0_id_width=12</TD>
    <TD>c_m_axi_gp0_thread_id_width=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_gp1_enable_static_remap=0</TD>
    <TD>c_m_axi_gp1_id_width=12</TD>
    <TD>c_m_axi_gp1_thread_id_width=12</TD>
    <TD>c_mio_primitive=54</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_f2p_intr_inputs=2</TD>
    <TD>c_package_name=clg400</TD>
    <TD>c_ps7_si_rev=PRODUCTION</TD>
    <TD>c_s_axi_acp_aruser_val=31</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_acp_awuser_val=31</TD>
    <TD>c_s_axi_acp_id_width=3</TD>
    <TD>c_s_axi_gp0_id_width=6</TD>
    <TD>c_s_axi_gp1_id_width=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_hp0_data_width=64</TD>
    <TD>c_s_axi_hp0_id_width=6</TD>
    <TD>c_s_axi_hp1_data_width=64</TD>
    <TD>c_s_axi_hp1_id_width=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_hp2_data_width=64</TD>
    <TD>c_s_axi_hp2_id_width=6</TD>
    <TD>c_s_axi_hp3_data_width=64</TD>
    <TD>c_s_axi_hp3_id_width=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_trace_buffer_clock_delay=12</TD>
    <TD>c_trace_buffer_fifo_size=128</TD>
    <TD>c_trace_internal_width=2</TD>
    <TD>c_trace_pipeline_width=8</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_axi_nonsecure=0</TD>
    <TD>c_use_default_acp_user_val=0</TD>
    <TD>c_use_m_axi_gp0=1</TD>
    <TD>c_use_m_axi_gp1=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_s_axi_acp=0</TD>
    <TD>c_use_s_axi_gp0=0</TD>
    <TD>c_use_s_axi_gp1=0</TD>
    <TD>c_use_s_axi_hp0=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_s_axi_hp1=0</TD>
    <TD>c_use_s_axi_hp2=0</TD>
    <TD>c_use_s_axi_hp3=0</TD>
    <TD>core_container=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>use_trace_data_edge_detector=0</TD>
    <TD>x_ipcorerevision=6</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=processing_system7</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=5.5</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_axi2sc_v1_0_7_top/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_arpayld_width=143</TD>
    <TD>c_awpayld_width=143</TD>
    <TD>c_axi_addr_width=32</TD>
    <TD>c_axi_id_width=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_rdata_width=32</TD>
    <TD>c_axi_wdata_width=32</TD>
    <TD>c_bpayld_width=7</TD>
    <TD>c_msc_route_width=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rpayld_width=53</TD>
    <TD>c_sc_addr_width=32</TD>
    <TD>c_sc_aruser_width=0</TD>
    <TD>c_sc_awuser_width=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_sc_buser_width=0</TD>
    <TD>c_sc_id_width=3</TD>
    <TD>c_sc_rdata_width=32</TD>
    <TD>c_sc_ruser_bits_per_byte=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_sc_wdata_width=32</TD>
    <TD>c_sc_wuser_bits_per_byte=0</TD>
    <TD>c_ssc_route_width=1</TD>
    <TD>c_wpayld_width=53</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=7</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_axi2sc</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_exit_v1_0_11_top/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_width=13</TD>
    <TD>c_enable_pipelining=0x1</TD>
    <TD>c_family=zynq</TD>
    <TD>c_has_lock=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_is_cascaded=0</TD>
    <TD>c_m_aruser_width=0</TD>
    <TD>c_m_awuser_width=0</TD>
    <TD>c_m_buser_width=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_id_width=0</TD>
    <TD>c_m_limit_read_length=16</TD>
    <TD>c_m_limit_write_length=16</TD>
    <TD>c_m_protocol=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_ruser_bits_per_byte=0</TD>
    <TD>c_m_ruser_width=0</TD>
    <TD>c_m_wuser_bits_per_byte=0</TD>
    <TD>c_m_wuser_width=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_max_ruser_bits_per_byte=0</TD>
    <TD>c_max_wuser_bits_per_byte=0</TD>
    <TD>c_mep_identifier_width=1</TD>
    <TD>c_num_msc=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_read_outstanding=8</TD>
    <TD>c_num_write_outstanding=8</TD>
    <TD>c_rdata_width=32</TD>
    <TD>c_read_acceptance=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_id_width=3</TD>
    <TD>c_single_issuing=0</TD>
    <TD>c_ssc_route_array=0b10</TD>
    <TD>c_ssc_route_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wdata_width=32</TD>
    <TD>c_write_acceptance=32</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipcorerevision=11</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_exit</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipproduct=Vivado 2020.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_exit_v1_0_11_top/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_width=13</TD>
    <TD>c_enable_pipelining=0x1</TD>
    <TD>c_family=zynq</TD>
    <TD>c_has_lock=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_is_cascaded=0</TD>
    <TD>c_m_aruser_width=0</TD>
    <TD>c_m_awuser_width=0</TD>
    <TD>c_m_buser_width=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_id_width=0</TD>
    <TD>c_m_limit_read_length=16</TD>
    <TD>c_m_limit_write_length=16</TD>
    <TD>c_m_protocol=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_ruser_bits_per_byte=0</TD>
    <TD>c_m_ruser_width=0</TD>
    <TD>c_m_wuser_bits_per_byte=0</TD>
    <TD>c_m_wuser_width=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_max_ruser_bits_per_byte=0</TD>
    <TD>c_max_wuser_bits_per_byte=0</TD>
    <TD>c_mep_identifier_width=1</TD>
    <TD>c_num_msc=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_read_outstanding=8</TD>
    <TD>c_num_write_outstanding=8</TD>
    <TD>c_rdata_width=32</TD>
    <TD>c_read_acceptance=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_id_width=3</TD>
    <TD>c_single_issuing=0</TD>
    <TD>c_ssc_route_array=0b10</TD>
    <TD>c_ssc_route_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wdata_width=32</TD>
    <TD>c_write_acceptance=32</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipcorerevision=11</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_exit</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipproduct=Vivado 2020.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_mmu_v1_0_10_top/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_width=32</TD>
    <TD>c_enable_pipelining=0x1</TD>
    <TD>c_family=zynq</TD>
    <TD>c_id_width=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_is_cascaded=0</TD>
    <TD>c_msc_route_array=0b1001</TD>
    <TD>c_msc_route_width=2</TD>
    <TD>c_num_msc=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_read_outstanding=8</TD>
    <TD>c_num_seg=2</TD>
    <TD>c_num_write_outstanding=8</TD>
    <TD>c_rdata_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_read_acceptance=32</TD>
    <TD>c_s_aruser_width=0</TD>
    <TD>c_s_awuser_width=0</TD>
    <TD>c_s_buser_width=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_protocol=1</TD>
    <TD>c_s_ruser_width=0</TD>
    <TD>c_s_wuser_width=0</TD>
    <TD>c_seg_base_addr_array=0x00000000410000000000000040000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_seg_secure_read_array=0b00</TD>
    <TD>c_seg_secure_write_array=0b00</TD>
    <TD>c_seg_sep_route_array=0x00000000000000010000000000000000</TD>
    <TD>c_seg_size_array=0x0000000d0000000d</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_seg_supports_read_array=0b11</TD>
    <TD>c_seg_supports_write_array=0b11</TD>
    <TD>c_single_issuing=0</TD>
    <TD>c_supports_narrow=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_supports_read_decerr=1</TD>
    <TD>c_supports_wrap=1</TD>
    <TD>c_supports_write_decerr=1</TD>
    <TD>c_wdata_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_write_acceptance=32</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_mmu</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/10</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aclk_relationship=1</TD>
    <TD>c_aclken_conversion=0</TD>
    <TD>c_addr_width=32</TD>
    <TD>c_arbiter_mode=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_channel=1</TD>
    <TD>c_disable_ip=0</TD>
    <TD>c_enable_pipelining=0x01</TD>
    <TD>c_family=zynq</TD>
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</TR><TR ALIGN='LEFT'>    <TD>c_user_width=0</TD>
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   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/11</B></TD></TR>
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   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/12</B></TD></TR>
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   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/13</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aclk_relationship=1</TD>
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</TR><TR ALIGN='LEFT'>    <TD>c_max_payld_bytes=4</TD>
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   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/14</B></TD></TR>
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</TR><TR ALIGN='LEFT'>    <TD>c_user_width=512</TD>
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   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/15</B></TD></TR>
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</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=53</TD>
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</TR><TR ALIGN='LEFT'>    <TD>c_user_width=512</TD>
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   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/1</B></TD></TR>
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</TR><TR ALIGN='LEFT'>    <TD>c_max_payld_bytes=4</TD>
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</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=143</TD>
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    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/2</B></TD></TR>
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    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/3</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aclk_relationship=1</TD>
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</TR><TR ALIGN='LEFT'>    <TD>c_max_payld_bytes=4</TD>
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    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/4</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aclk_relationship=1</TD>
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</TR><TR ALIGN='LEFT'>    <TD>c_max_payld_bytes=4</TD>
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    <TD>c_s_num_bytes_array=0x00000004</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_pipeline=0</TD>
    <TD>c_sc_route_width=1</TD>
    <TD>c_synchronization_stages=3</TD>
    <TD>c_user_bits_per_byte=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_user_width=0</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_node</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/5</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aclk_relationship=1</TD>
    <TD>c_aclken_conversion=0</TD>
    <TD>c_addr_width=32</TD>
    <TD>c_arbiter_mode=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_channel=1</TD>
    <TD>c_disable_ip=0</TD>
    <TD>c_enable_pipelining=0x01</TD>
    <TD>c_family=zynq</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_fifo_ip=0</TD>
    <TD>c_fifo_output_reg=1</TD>
    <TD>c_fifo_size=5</TD>
    <TD>c_fifo_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_id_width=3</TD>
    <TD>c_m_num_bytes_array=0x0000000400000004</TD>
    <TD>c_m_pipeline=0</TD>
    <TD>c_m_send_pipeline=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_max_payld_bytes=4</TD>
    <TD>c_num_mi=1</TD>
    <TD>c_num_outstanding=8</TD>
    <TD>c_num_si=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=53</TD>
    <TD>c_priority_arb_array=0b0</TD>
    <TD>c_s_latency=1</TD>
    <TD>c_s_num_bytes_array=0x00000004</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_pipeline=0</TD>
    <TD>c_sc_route_width=2</TD>
    <TD>c_synchronization_stages=3</TD>
    <TD>c_user_bits_per_byte=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_user_width=0</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_node</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/6</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aclk_relationship=1</TD>
    <TD>c_aclken_conversion=0</TD>
    <TD>c_addr_width=32</TD>
    <TD>c_arbiter_mode=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_channel=2</TD>
    <TD>c_disable_ip=0</TD>
    <TD>c_enable_pipelining=0x01</TD>
    <TD>c_family=zynq</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_fifo_ip=0</TD>
    <TD>c_fifo_output_reg=1</TD>
    <TD>c_fifo_size=5</TD>
    <TD>c_fifo_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_id_width=3</TD>
    <TD>c_m_num_bytes_array=0x0000000400000004</TD>
    <TD>c_m_pipeline=0</TD>
    <TD>c_m_send_pipeline=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_max_payld_bytes=4</TD>
    <TD>c_num_mi=1</TD>
    <TD>c_num_outstanding=8</TD>
    <TD>c_num_si=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=143</TD>
    <TD>c_priority_arb_array=0b0</TD>
    <TD>c_s_latency=1</TD>
    <TD>c_s_num_bytes_array=0x00000004</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_pipeline=0</TD>
    <TD>c_sc_route_width=2</TD>
    <TD>c_synchronization_stages=3</TD>
    <TD>c_user_bits_per_byte=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_user_width=0</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_node</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/7</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aclk_relationship=1</TD>
    <TD>c_aclken_conversion=0</TD>
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</TR><TR ALIGN='LEFT'>    <TD>c_channel=3</TD>
    <TD>c_disable_ip=0</TD>
    <TD>c_enable_pipelining=0x01</TD>
    <TD>c_family=zynq</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_fifo_ip=0</TD>
    <TD>c_fifo_output_reg=1</TD>
    <TD>c_fifo_size=5</TD>
    <TD>c_fifo_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_id_width=3</TD>
    <TD>c_m_num_bytes_array=0x0000000400000004</TD>
    <TD>c_m_pipeline=0</TD>
    <TD>c_m_send_pipeline=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_max_payld_bytes=4</TD>
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    <TD>c_num_outstanding=8</TD>
    <TD>c_num_si=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=143</TD>
    <TD>c_priority_arb_array=0b0</TD>
    <TD>c_s_latency=1</TD>
    <TD>c_s_num_bytes_array=0x00000004</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_pipeline=0</TD>
    <TD>c_sc_route_width=2</TD>
    <TD>c_synchronization_stages=3</TD>
    <TD>c_user_bits_per_byte=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_user_width=0</TD>
    <TD>core_container=NA</TD>
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    <TD>x_ipcorerevision=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_node</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
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</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/8</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aclk_relationship=1</TD>
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</TR><TR ALIGN='LEFT'>    <TD>c_channel=4</TD>
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    <TD>c_family=zynq</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_fifo_ip=0</TD>
    <TD>c_fifo_output_reg=1</TD>
    <TD>c_fifo_size=5</TD>
    <TD>c_fifo_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_id_width=3</TD>
    <TD>c_m_num_bytes_array=0x0000000400000004</TD>
    <TD>c_m_pipeline=0</TD>
    <TD>c_m_send_pipeline=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_max_payld_bytes=4</TD>
    <TD>c_num_mi=1</TD>
    <TD>c_num_outstanding=8</TD>
    <TD>c_num_si=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=7</TD>
    <TD>c_priority_arb_array=0b0</TD>
    <TD>c_s_latency=0</TD>
    <TD>c_s_num_bytes_array=0x00000004</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_pipeline=0</TD>
    <TD>c_sc_route_width=1</TD>
    <TD>c_synchronization_stages=3</TD>
    <TD>c_user_bits_per_byte=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_user_width=0</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_node</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
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</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_node_v1_0_12_top/9</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aclk_relationship=1</TD>
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    <TD>c_arbiter_mode=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_channel=0</TD>
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    <TD>c_family=zynq</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_fifo_ip=0</TD>
    <TD>c_fifo_output_reg=1</TD>
    <TD>c_fifo_size=5</TD>
    <TD>c_fifo_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_id_width=3</TD>
    <TD>c_m_num_bytes_array=0x0000000400000004</TD>
    <TD>c_m_pipeline=0</TD>
    <TD>c_m_send_pipeline=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_max_payld_bytes=4</TD>
    <TD>c_num_mi=1</TD>
    <TD>c_num_outstanding=8</TD>
    <TD>c_num_si=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=53</TD>
    <TD>c_priority_arb_array=0b0</TD>
    <TD>c_s_latency=0</TD>
    <TD>c_s_num_bytes_array=0x00000004</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_pipeline=0</TD>
    <TD>c_sc_route_width=1</TD>
    <TD>c_synchronization_stages=3</TD>
    <TD>c_user_bits_per_byte=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_user_width=0</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_node</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_sc2axi_v1_0_7_top/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_arpayld_width=143</TD>
    <TD>c_awpayld_width=143</TD>
    <TD>c_axi_addr_width=13</TD>
    <TD>c_axi_id_width=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_rdata_width=32</TD>
    <TD>c_axi_wdata_width=32</TD>
    <TD>c_bpayld_width=7</TD>
    <TD>c_msc_route_width=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rpayld_width=53</TD>
    <TD>c_sc_addr_width=32</TD>
    <TD>c_sc_aruser_width=0</TD>
    <TD>c_sc_awuser_width=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_sc_buser_width=0</TD>
    <TD>c_sc_id_width=3</TD>
    <TD>c_sc_rdata_width=32</TD>
    <TD>c_sc_ruser_bits_per_byte=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_sc_wdata_width=32</TD>
    <TD>c_sc_wuser_bits_per_byte=0</TD>
    <TD>c_ssc_route_width=1</TD>
    <TD>c_wpayld_width=53</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=7</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_sc2axi</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_sc2axi_v1_0_7_top/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_arpayld_width=143</TD>
    <TD>c_awpayld_width=143</TD>
    <TD>c_axi_addr_width=13</TD>
    <TD>c_axi_id_width=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_rdata_width=32</TD>
    <TD>c_axi_wdata_width=32</TD>
    <TD>c_bpayld_width=7</TD>
    <TD>c_msc_route_width=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rpayld_width=53</TD>
    <TD>c_sc_addr_width=32</TD>
    <TD>c_sc_aruser_width=0</TD>
    <TD>c_sc_awuser_width=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_sc_buser_width=0</TD>
    <TD>c_sc_id_width=3</TD>
    <TD>c_sc_rdata_width=32</TD>
    <TD>c_sc_ruser_bits_per_byte=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_sc_wdata_width=32</TD>
    <TD>c_sc_wuser_bits_per_byte=0</TD>
    <TD>c_ssc_route_width=1</TD>
    <TD>c_wpayld_width=53</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=7</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_sc2axi</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_si_converter_v1_0_10_top/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_width=32</TD>
    <TD>c_axilite_conv=0</TD>
    <TD>c_enable_pipelining=0x1</TD>
    <TD>c_has_burst=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_id_width=3</TD>
    <TD>c_is_cascaded=0</TD>
    <TD>c_limit_read_length=0</TD>
    <TD>c_limit_write_length=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_max_ruser_bits_per_byte=0</TD>
    <TD>c_max_wuser_bits_per_byte=0</TD>
    <TD>c_mep_identifier_width=1</TD>
    <TD>c_msc_rdata_width_array=0x0000002000000020</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_msc_wdata_width_array=0x0000002000000020</TD>
    <TD>c_num_msc=2</TD>
    <TD>c_num_read_outstanding=8</TD>
    <TD>c_num_read_threads=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_seg=2</TD>
    <TD>c_num_write_outstanding=8</TD>
    <TD>c_num_write_threads=4</TD>
    <TD>c_rdata_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_read_acceptance=32</TD>
    <TD>c_read_watermark=0</TD>
    <TD>c_s_ruser_bits_per_byte=0</TD>
    <TD>c_s_wuser_bits_per_byte=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_sep_protocol_array=0x0000000000000000</TD>
    <TD>c_sep_rdata_width_array=0x0000002000000020</TD>
    <TD>c_sep_wdata_width_array=0x0000002000000020</TD>
    <TD>c_single_issuing=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_supports_narrow=0</TD>
    <TD>c_wdata_width=32</TD>
    <TD>c_write_acceptance=32</TD>
    <TD>c_write_watermark=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=10</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_si_converter</TD>
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    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
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</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_switchboard_v1_0_6_top/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_connectivity=0b11</TD>
    <TD>c_m_pipelines=1</TD>
    <TD>c_num_mi=2</TD>
    <TD>c_num_si=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=143</TD>
    <TD>c_s_latency=0</TD>
    <TD>c_s_pipelines=0</TD>
    <TD>c_testing_mode=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>k_max_info_width=1</TD>
    <TD>x_ipcorerevision=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_switchboard</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_switchboard_v1_0_6_top/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_connectivity=0b11</TD>
    <TD>c_m_pipelines=1</TD>
    <TD>c_num_mi=2</TD>
    <TD>c_num_si=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=143</TD>
    <TD>c_s_latency=0</TD>
    <TD>c_s_pipelines=0</TD>
    <TD>c_testing_mode=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>k_max_info_width=1</TD>
    <TD>x_ipcorerevision=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_switchboard</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_switchboard_v1_0_6_top/3</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_connectivity=11</TD>
    <TD>c_m_pipelines=1</TD>
    <TD>c_num_mi=1</TD>
    <TD>c_num_si=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=7</TD>
    <TD>c_s_latency=0</TD>
    <TD>c_s_pipelines=0</TD>
    <TD>c_testing_mode=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>k_max_info_width=1</TD>
    <TD>x_ipcorerevision=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_switchboard</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_switchboard_v1_0_6_top/4</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_connectivity=11</TD>
    <TD>c_m_pipelines=1</TD>
    <TD>c_num_mi=1</TD>
    <TD>c_num_si=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=53</TD>
    <TD>c_s_latency=0</TD>
    <TD>c_s_pipelines=0</TD>
    <TD>c_testing_mode=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>k_max_info_width=1</TD>
    <TD>x_ipcorerevision=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_switchboard</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_switchboard_v1_0_6_top/5</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_connectivity=0b11</TD>
    <TD>c_m_pipelines=1</TD>
    <TD>c_num_mi=2</TD>
    <TD>c_num_si=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_payld_width=53</TD>
    <TD>c_s_latency=0</TD>
    <TD>c_s_pipelines=0</TD>
    <TD>c_testing_mode=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>k_max_info_width=1</TD>
    <TD>x_ipcorerevision=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_switchboard</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>sc_transaction_regulator_v1_0_9_top/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_width=32</TD>
    <TD>c_enable_pipelining=0x1</TD>
    <TD>c_family=zynq</TD>
    <TD>c_is_cascaded=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_id_width=3</TD>
    <TD>c_mep_identifier=1</TD>
    <TD>c_mep_identifier_width=1</TD>
    <TD>c_num_read_outstanding=8</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_read_threads=4</TD>
    <TD>c_num_write_outstanding=8</TD>
    <TD>c_num_write_threads=4</TD>
    <TD>c_rdata_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_read_acceptance=32</TD>
    <TD>c_s_id_width=12</TD>
    <TD>c_sep_route_width=1</TD>
    <TD>c_single_issuing=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_supports_read_deadlock=1</TD>
    <TD>c_supports_write_deadlock=1</TD>
    <TD>c_wdata_width=32</TD>
    <TD>c_write_acceptance=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=9</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=sc_transaction_regulator</TD>
    <TD>x_ipproduct=Vivado 2020.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xpm_cdc_async_rst/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>def_val=1&apos;b1</TD>
    <TD>dest_sync_ff=3</TD>
    <TD>init_sync_ff=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>inv_def_val=1&apos;b0</TD>
    <TD>iptotal=20</TD>
    <TD>rst_active_high=0</TD>
    <TD>version=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xpm_memory_base/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>version=0</TD>
    <TD>addr_width_a=5</TD>
    <TD>addr_width_b=5</TD>
    <TD>auto_sleep_time=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>byte_write_width_a=53</TD>
    <TD>byte_write_width_b=53</TD>
    <TD>cascade_height=0</TD>
    <TD>clocking_mode=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>ecc_mode=0</TD>
    <TD>iptotal=18</TD>
    <TD>max_num_char=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>memory_optimization=true</TD>
    <TD>memory_primitive=1</TD>
    <TD>memory_size=1696</TD>
    <TD>memory_type=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>message_control=0</TD>
    <TD>num_char_loc=0</TD>
    <TD>p_ecc_mode=no_ecc</TD>
    <TD>p_enable_byte_write_a=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>p_enable_byte_write_b=0</TD>
    <TD>p_max_depth_data=32</TD>
    <TD>p_memory_opt=yes</TD>
    <TD>p_memory_primitive=distributed</TD>
</TR><TR ALIGN='LEFT'>    <TD>p_min_width_data=53</TD>
    <TD>p_min_width_data_a=53</TD>
    <TD>p_min_width_data_b=53</TD>
    <TD>p_min_width_data_ecc=53</TD>
</TR><TR ALIGN='LEFT'>    <TD>p_min_width_data_ldw=4</TD>
    <TD>p_min_width_data_shft=53</TD>
    <TD>p_num_cols_write_a=1</TD>
    <TD>p_num_cols_write_b=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>p_num_rows_read_a=1</TD>
    <TD>p_num_rows_read_b=1</TD>
    <TD>p_num_rows_write_a=1</TD>
    <TD>p_num_rows_write_b=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>p_sdp_write_mode=yes</TD>
    <TD>p_width_addr_lsb_read_a=0</TD>
    <TD>p_width_addr_lsb_read_b=0</TD>
    <TD>p_width_addr_lsb_write_a=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>p_width_addr_lsb_write_b=0</TD>
    <TD>p_width_addr_read_a=5</TD>
    <TD>p_width_addr_read_b=5</TD>
    <TD>p_width_addr_write_a=5</TD>
</TR><TR ALIGN='LEFT'>    <TD>p_width_addr_write_b=5</TD>
    <TD>p_width_col_write_a=53</TD>
    <TD>p_width_col_write_b=53</TD>
    <TD>read_data_width_a=53</TD>
</TR><TR ALIGN='LEFT'>    <TD>read_data_width_b=53</TD>
    <TD>read_latency_a=2</TD>
    <TD>read_latency_b=1</TD>
    <TD>read_reset_value_a=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>read_reset_value_b=0</TD>
    <TD>rst_mode_a=SYNC</TD>
    <TD>rst_mode_b=SYNC</TD>
    <TD>rsta_loop_iter=56</TD>
</TR><TR ALIGN='LEFT'>    <TD>rstb_loop_iter=56</TD>
    <TD>sim_assert_chk=0</TD>
    <TD>use_embedded_constraint=0</TD>
    <TD>use_mem_init=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_mem_init_mmi=0</TD>
    <TD>version=0</TD>
    <TD>wakeup_time=0</TD>
    <TD>write_data_width_a=53</TD>
</TR><TR ALIGN='LEFT'>    <TD>write_data_width_b=53</TD>
    <TD>write_mode_a=1</TD>
    <TD>write_mode_b=1</TD>
    <TD>write_protect=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xpm_memory_sdpram/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>write_protect=1</TD>
    <TD>addr_width_a=5</TD>
    <TD>addr_width_b=5</TD>
    <TD>auto_sleep_time=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>byte_write_width_a=53</TD>
    <TD>cascade_height=0</TD>
    <TD>clocking_mode=0</TD>
    <TD>core_container=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>ecc_mode=0</TD>
    <TD>iptotal=18</TD>
    <TD>memory_optimization=true</TD>
    <TD>memory_primitive=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>memory_size=1696</TD>
    <TD>message_control=0</TD>
    <TD>p_clocking_mode=0</TD>
    <TD>p_ecc_mode=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>p_memory_optimization=1</TD>
    <TD>p_memory_primitive=1</TD>
    <TD>p_wakeup_time=0</TD>
    <TD>p_write_mode_b=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>read_data_width_b=53</TD>
    <TD>read_latency_b=1</TD>
    <TD>read_reset_value_b=0</TD>
    <TD>rst_mode_a=SYNC</TD>
</TR><TR ALIGN='LEFT'>    <TD>rst_mode_b=SYNC</TD>
    <TD>sim_assert_chk=0</TD>
    <TD>use_embedded_constraint=0</TD>
    <TD>use_mem_init=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_mem_init_mmi=0</TD>
    <TD>wakeup_time=0</TD>
    <TD>write_data_width_a=53</TD>
    <TD>write_mode_b=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>write_protect=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-internal=default::[not_specified]</TD>
    <TD>-internal_only=default::[not_specified]</TD>
    <TD>-max_msgs_per_check=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_waivers=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-ruledecks=default::[not_specified]</TD>
    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=1</TD>
    <TD>bufgctrl_util_percentage=3.13</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=48</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=8</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=4</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=8</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=2</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_used=0</TD>
    <TD>mmcme2_adv_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=2</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=80</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=0</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=1</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=1</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=1</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=60</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=2</TD>
    <TD>block_ram_tile_util_percentage=3.33</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=120</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=0</TD>
    <TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_available=60</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=2</TD>
    <TD>ramb36_fifo_util_percentage=3.33</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36e1_only_used=2</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bibuf_functional_category=IO</TD>
    <TD>bibuf_used=130</TD>
    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=20</TD>
    <TD>fdce_functional_category=Flop &amp; Latch</TD>
    <TD>fdce_used=60</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=4121</TD>
    <TD>fdse_functional_category=Flop &amp; Latch</TD>
    <TD>fdse_used=259</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=192</TD>
    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=344</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=972</TD>
    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=758</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=786</TD>
    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=1501</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf7_functional_category=MuxFx</TD>
    <TD>muxf7_used=4</TD>
    <TD>ps7_functional_category=Specialized Resource</TD>
    <TD>ps7_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36e1_functional_category=Block Memory</TD>
    <TD>ramb36e1_used=2</TD>
    <TD>ramd32_functional_category=Distributed Memory</TD>
    <TD>ramd32_used=468</TD>
</TR><TR ALIGN='LEFT'>    <TD>rams32_functional_category=Distributed Memory</TD>
    <TD>rams32_used=156</TD>
    <TD>srl16e_functional_category=Distributed Memory</TD>
    <TD>srl16e_used=141</TD>
</TR><TR ALIGN='LEFT'>    <TD>srlc32e_functional_category=Distributed Memory</TD>
    <TD>srlc32e_used=182</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=8800</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=4</TD>
    <TD>f7_muxes_util_percentage=0.05</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=4400</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=0</TD>
    <TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=312</TD>
    <TD>lut_as_logic_available=17600</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=3547</TD>
    <TD>lut_as_logic_util_percentage=20.15</TD>
    <TD>lut_as_memory_available=6000</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=635</TD>
    <TD>lut_as_memory_util_percentage=10.58</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=323</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=35200</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=4440</TD>
    <TD>register_as_flip_flop_util_percentage=12.61</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=35200</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=17600</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=4182</TD>
    <TD>slice_luts_util_percentage=23.76</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=35200</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=4440</TD>
    <TD>slice_registers_util_percentage=12.61</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=312</TD>
    <TD>lut_as_logic_available=17600</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=3547</TD>
    <TD>lut_as_logic_util_percentage=20.15</TD>
    <TD>lut_as_memory_available=6000</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=635</TD>
    <TD>lut_as_memory_util_percentage=10.58</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=323</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_in_front_of_the_register_is_unused_fixed=323</TD>
    <TD>lut_in_front_of_the_register_is_unused_used=1091</TD>
    <TD>lut_in_front_of_the_register_is_used_fixed=1091</TD>
    <TD>lut_in_front_of_the_register_is_used_used=267</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_driven_from_outside_the_slice_fixed=267</TD>
    <TD>register_driven_from_outside_the_slice_used=1358</TD>
    <TD>register_driven_from_within_the_slice_fixed=1358</TD>
    <TD>register_driven_from_within_the_slice_used=3082</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_available=4400</TD>
    <TD>slice_fixed=0</TD>
    <TD>slice_registers_available=35200</TD>
    <TD>slice_registers_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_used=4440</TD>
    <TD>slice_registers_util_percentage=12.61</TD>
    <TD>slice_used=1560</TD>
    <TD>slice_util_percentage=35.45</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=1003</TD>
    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=557</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_available=4400</TD>
    <TD>unique_control_sets_fixed=4400</TD>
    <TD>unique_control_sets_used=340</TD>
    <TD>unique_control_sets_util_percentage=7.73</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_fixed=7.73</TD>
    <TD>using_o5_and_o6_used=0</TD>
    <TD>using_o5_output_only_fixed=0</TD>
    <TD>using_o5_output_only_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_fixed=2</TD>
    <TD>using_o6_output_only_used=321</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=0</TD>
    <TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-debug_log=default::[not_specified]</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
</TR><TR ALIGN='LEFT'>    <TD>-flatten_hierarchy=default::rebuilt</TD>
    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-include_dirs=default::[not_specified]</TD>
    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-lint=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-os=default::[not_specified]</TD>
    <TD>-part=xc7z010clg400-1</TD>
    <TD>-resource_sharing=default::auto</TD>
</TR><TR ALIGN='LEFT'>    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
    <TD>-rtl_skip_ip=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
    <TD>-top=design_1_wrapper</TD>
</TR><TR ALIGN='LEFT'>    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:02:22s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=905.008MB</TD>
    <TD>memory_peak=2048.543MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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